A Survey of Network-Based Hardware Accelerators

Many practical data-processing algorithms fail to execute efficiently on general-purpose CPUs (Central Processing Units) due the sequential matter of their operations and memory bandwidth limitations. To achieve desired performance levels, reconfigurable (FPGA (Field-Programmable Gate Array)-based) hardware accelerators are frequently explored that permit processing units’ architectures be better adapted specific problem/algorithm requirements. In particular, network-based very well suited implementation in because several data-independent can easily naturally executed parallel over as many blocks actually required technically possible. GPUs (Graphics have also demonstrated good results this area but they tend use significantly more power than FPGA, which could a limiting factor embedded applications. Moreover, employ Single Instruction, Multiple Threads (SIMT) execution model therefore optimized SIMD (Single Data) operations, while FPGAs fully custom datapaths built, eliminating much control overhead. This review paper aims analyze, compare, discuss different approaches implementing FPGA programmable SoC (Systems-on-Chip). The performed analysis derived recommendations would useful designers future accelerators.